Connectivity - SPI - nordic,nrf-spim
nRF5340 SPIM (SPI master with EasyDMA)
Behavioral SPIM model with no real SPI bus: `TASKS_START` fires `STARTED` immediately, queues the TXD/RXD EasyDMA transfers (RX is filled with the `ORC` idle byte), and latches `ENDTX`, `ENDRX`, and `END` in the same write cycle (IRQ when enabled). DPPI subscribe/publish is supported; the `END_START` short does not auto-restart in emulation. A `nrf.spim.transfer` custom event is emitted on every transfer so the host can observe SPI traffic.
Events emitted
nrf.spim.transferFires when a SPIM EasyDMA transfer completes (END event). Carries the TX pointer, TX byte count, RX pointer, and RX byte count.
Payload
| Field | Type | Description |
|---|---|---|
rxd_amount | u32 | Number of RX bytes received (filled with ORC). |
rxd_ptr | u32 | RX DMA destination pointer in guest SRAM. |
txd_amount | u32 | Number of TX bytes transferred. |
txd_ptr | u32 | TX DMA source pointer in guest SRAM. |
Events accepted
No peripheral-specific input events. The peripheral is driven through MMIO register access.
Commands
This peripheral exposes no commands.
Snapshot fields
| Field | Type | Label |
|---|---|---|
| inten | u32 | INTEN (interrupt enable mask) |
| ev_stopped | u32 | EVENTS_STOPPED latch |
| ev_endrx | u32 | EVENTS_ENDRX latch |
| ev_end | u32 | EVENTS_END latch |
| ev_endtx | u32 | EVENTS_ENDTX latch |
| ev_started | u32 | EVENTS_STARTED latch |
| enable | u32 | ENABLE register |
| frequency | u32 | FREQUENCY register |
| config | u32 | CONFIG register (CPHA/CPOL/ORDER) |
| orc | u32 | ORC (over-run character) |
| txd_ptr | u32 | TXD.PTR |
| txd_maxcnt | u32 | TXD.MAXCNT |
| txd_amount | u32 | TXD.AMOUNT |
| rxd_ptr | u32 | RXD.PTR |
| rxd_maxcnt | u32 | RXD.MAXCNT |
| rxd_amount | u32 | RXD.AMOUNT |
| state_json | str | SPIM State Summary (JSON) |
Read at runtime with emulator.peripheral_snapshot(name).