Multi-core & SMP
0 done - 2 partial - 5 to build
Why it matters
Concurrent/lockstep multi-core execution, PSCI bring-up, affinity and coherency.
What
Build out the 'Multi-core & SMP' capability area: 7 stories spanning 2 not-yet-built, 3 stubbed, 2 partial and 0 already-implemented (hardening) features.
Stories in this epic (7)
- Multi-core / SMP scheduling$0 / $8,750 - 0%Stub
- PSCI secondary-core boot (CPU_ON)$0 / $5,500 - 0%Stub
- Asymmetric multi-core (e.g. nRF5340 app+net)$0 / $4,000 - 0%Partial
- GIC per-core redistributor / affinity$0 / $4,000 - 0%Partial
- NUMA modeling$0 / $8,000 - 0%Not implemented
- Cache coherency between cores$0 / $12,750 - 0%Not implemented
- Deterministic SMP quantum stepper$0 / $8,750 - 0%Stub
Activity log
Feature defined and added to the roadmap
Feature defined and added to the roadmap
Feature defined and added to the roadmap
Feature defined and added to the roadmap
Feature defined and added to the roadmap
Feature defined and added to the roadmap
Feature defined and added to the roadmap
Funding goal set to $4,000
Funding goal set to $12,750
Funding goal set to $8,750
Funding goal set to $4,000
Funding goal set to $8,750
Funding goal set to $8,000
Funding goal set to $5,500
Implementation status: Partial
Implementation status: Not implemented
Implementation status: Stub
Implementation status: Partial
Implementation status: Stub
Implementation status: Not implemented
Implementation status: Stub