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Not implemented

Cache coherency between cores

Priority 8 - Multi-Core, SMP & System Integration

$0 / $12,7500% funded
Fund$12,750
$0 / $12,750 - 0%
As an operating-system developer, I want vemu to finish its Cache coherency between cores model, so that I can depend on SMP correctness for production firmware, not just the common path.

Why it matters

SMP correctness

Summary

Snoop/MESI behavior

Scope of work

Not present today. Deliver a behavioral model of Cache coherency between cores. What it is: Snoop/MESI behavior. Why it matters: SMP correctness.

Current state

Status: Not implemented. Notes / evidence: No caches at all.

Blocked by 2

Fund these first - this work can't be completed until they ship.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $12,750

  3. Implementation status: Not implemented