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Stub

Deterministic SMP quantum stepper

Priority 8 - Multi-Core, SMP & System Integration

$0 / $8,7500% funded
Fund$8,750
$0 / $8,750 - 0%
As an operating-system developer, I want vemu to finish its Deterministic SMP quantum stepper model, so that I can depend on replayable SMP for production firmware, not just the common path.

Why it matters

Replayable SMP

Summary

Reproducible interleaving

Scope of work

Currently a register-only stub. Replace it with a working model of Deterministic SMP quantum stepper that actually exhibits the hardware behavior. What it is: Reproducible interleaving. Why it matters: Replayable SMP.

Current state

Status: Stub only (registers, no behavior). Notes / evidence: No SMP quantum interleaver exists; the deterministic step counter (cortex-a bus.rs) is a per-core clock for JIT/interpreter lockstep, not a multi-core round-robin scheduler.

Blocked by 2

Fund these first - this work can't be completed until they ship.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $8,750

  3. Implementation status: Stub