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Not implemented

x86 interrupt controllers (PIC/PIT/APIC/IOAPIC)

Priority 1 - CPU Architectures & Execution Engines / 1.5 x86

$0 / $15,7500% funded
Fund$15,750
$0 / $15,750 - 0%
As a firmware developer, I want vemu to finish its x86 interrupt controllers (PIC/PIT/APIC/IOAPIC) model, so that I can depend on x86 OS for production firmware, not just the common path.

Why it matters

x86 OS

Summary

Legacy + modern IRQ

Scope of work

Not present today. Deliver a behavioral model of x86 interrupt controllers (PIC/PIT/APIC/IOAPIC). What it is: Legacy + modern IRQ. Why it matters: x86 OS.

Current state

Status: Not implemented. Notes / evidence: No in-board chipset.

Blocked by 1

Fund these first - this work can't be completed until they ship.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $15,750

  3. Implementation status: Not implemented