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Implemented

System registers (core set, GICv3 ICC, timers)

Priority 1 - CPU Architectures & Execution Engines / 1.3 AArch64 (A64) & Cortex-A 64-bit

$2,250 / $2,250fully funded
Done$2,250 / $2,250 - 100%
As a firmware developer, I want vemu's System registers (core set, GICv3 ICC, timers) to stay accurate, tested, and documented, so that I can keep depending on OS bring-up.

Why it matters

OS bring-up

Summary

MRS/MSR

Scope of work

Already implemented. Harden, broaden coverage, add tests and documentation for System registers (core set, GICv3 ICC, timers). What it is: MRS/MSR. Why it matters: OS bring-up.

Current state

Status: Fully implemented. Notes / evidence: PMU/debug RAZ/WI.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 4

Funding this also clears the way for the work below.

  • Done
  • Done
  • Fund$8,000
  • Fund$8,000

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $2,250

  3. Implementation status: Implemented

  4. Delivered - counted as fully funded