← Back to roadmap
Partial

SWD (line reset, ACK, parity)

Priority 3 - Debug, Trace & Instrumentation Hardware / 3.1 Debug transport & probe protocols

$0 / $4,0000% funded
Fund$4,000
$0 / $4,000 - 0%
As a firmware debugger, I want vemu to finish its SWD (line reset, ACK, parity) model, so that I can depend on cortex debug for production firmware, not just the common path.

Why it matters

Cortex debug

Summary

2-wire ARM debug

Scope of work

Partially modeled. Complete the missing mechanics of SWD (line reset, ACK, parity). What it is: 2-wire ARM debug. Why it matters: Cortex debug.

Current state

Status: Partially implemented. Notes / evidence: swd.rs decodes the request packet + parity + ACK codes only; no line-reset / JTAG-to-SWD switch sequence or data-phase state machine.

Unblocks 1

Funding this also clears the way for the work below.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $4,000

  3. Implementation status: Partial