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Partial

STM32 GTZC (TZSC / TZIC / MPCBB)

STMicroelectronics STM32 program

$0 / $2,7500% funded
Fund$2,750
$0 / $2,750 - 0%
As an embedded developer, I want vemu to model STM32 GTZC (TZSC / TZIC / MPCBB), so that I can build and test firmware that needs STM32U5/L5/H5 secure/non-secure isolation that TF-M and secure firmware rely on long before the hardware is in hand.

Why it matters

STM32U5/L5/H5 secure/non-secure isolation that TF-M and secure firmware rely on

Summary

Global TrustZone Controller: securable peripheral gating (TZSC), illegal-access interrupts (TZIC) and block-based RAM protection (MPCBB)

Scope of work

Not present today. Deliver a behavioral model of STM32 GTZC (TZSC / TZIC / MPCBB). What it is: Global TrustZone Controller: securable peripheral gating (TZSC), illegal-access interrupts (TZIC) and block-based RAM protection (MPCBB). Why it matters: STM32U5/L5/H5 secure/non-secure isolation that TF-M and secure firmware rely on.

Current state

Status: partial. Notes / evidence: STM32-specific IP modeled in crates/vemu-soc-st; no generic story covers it.

Blocked by 4

Fund these first - this work can't be completed until they ship.

  • Done
  • Done
  • Done
  • Done
Unblocks 2

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $2,750

  3. Implementation status: Partial