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Partial

SD/eMMC host controller

Priority 6 - Storage Controllers & Memory Devices

$0 / $4,0000% funded
Fund$4,000
$0 / $4,000 - 0%
As a firmware developer, I want vemu to finish its SD/eMMC host controller model, so that I can depend on mass storage for production firmware, not just the common path.

Why it matters

Mass storage

Summary

Command set + DMA + card backend

Scope of work

Partially modeled. Complete the missing mechanics of SD/eMMC host controller. What it is: Command set + DMA + card backend. Why it matters: Mass storage.

Current state

Status: Partially implemented. Notes / evidence: RK MSHC real read path (CMD17/18 + IDMAC scatter to guest RAM); writes NOT persisted (CMD24/25 latch the LBA but write_sector is never called); STM32 SDMMC is a register stub.

Blocked by 2

Fund these first - this work can't be completed until they ship.

  • Done
  • Done
Unblocks 6

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $4,000

  3. Implementation status: Partial