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Implemented

RV64I base integer ISA

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$2,000 / $2,000fully funded
Done$2,000 / $2,000 - 100%
As a firmware developer, I want vemu's RV64I base integer ISA to stay accurate, tested, and documented, so that I can keep depending on 64-bit Linux/RTOS on RISC-V.

Why it matters

64-bit Linux/RTOS on RISC-V

Summary

Base integer LUI/AUIPC/branch/load/store/OP

Scope of work

Already implemented. Harden, broaden coverage, add tests and documentation for RV64I base integer ISA. What it is: Base integer LUI/AUIPC/branch/load/store/OP. Why it matters: 64-bit Linux/RTOS on RISC-V.

Current state

Status: Fully implemented. Notes / evidence: vemu-arch-riscv64/src/decoder.rs + cpu.rs; rv64ui conformance suite passes.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 9

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $2,000

  3. Implementation status: Implemented

  4. Delivered - counted as fully funded