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Implemented

Zicsr CSRs + M/S/U privilege & traps

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$2,500 / $2,500fully funded
Done$2,500 / $2,500 - 100%
As a firmware developer, I want vemu's Zicsr CSRs + M/S/U privilege & traps to stay accurate, tested, and documented, so that I can keep depending on OS kernels and trap handling.

Why it matters

OS kernels and trap handling

Summary

CSRs with M/S/U traps and interrupts

Scope of work

Already implemented. Harden, broaden coverage, add tests and documentation for Zicsr CSRs + M/S/U privilege & traps. What it is: CSRs with M/S/U traps and interrupts. Why it matters: OS kernels and trap handling.

Current state

Status: Fully implemented. Notes / evidence: csr.rs full M/S/U set (incl. T-HEAD CSRs); trap.rs exception/interrupt model.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 2

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $2,500

  3. Implementation status: Implemented

  4. Delivered - counted as fully funded