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Partial

RVV 0.7.1 vector (T-HEAD)

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$0 / $8,0000% funded
Fund$8,000
$0 / $8,000 - 0%
As a firmware developer, I want vemu to finish its RVV 0.7.1 vector (T-HEAD) model, so that I can depend on DSP and ML kernels for production firmware, not just the common path.

Why it matters

DSP and ML kernels

Summary

T-HEAD RVV 0.7.1 vector unit

Scope of work

Partially modeled. Complete the missing mechanics of RVV 0.7.1 vector (T-HEAD). What it is: T-HEAD RVV 0.7.1 vector unit. Why it matters: DSP and ML kernels.

Current state

Status: Partially implemented. Notes / evidence: vector.rs: unit/strided load-store, integer arithmetic, reductions, masking with vstart. TODO: FP-vector, fixed-point, narrowing, indexed/segment, mask-logical, slides, vrgather.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 1

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $8,000

  3. Implementation status: Partial