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Not implemented

Sv48 4-level paging

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$0 / $5,2500% funded
Fund$5,250
$0 / $5,250 - 0%
As a firmware developer, I want vemu to finish its Sv48 4-level paging model, so that I can depend on large address spaces for production firmware, not just the common path.

Why it matters

large address spaces

Summary

Sv48 4-level page tables

Scope of work

Not present today. Deliver a behavioral model of Sv48 4-level paging. Why it matters: large address spaces.

Current state

Status: Not implemented.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $5,250

  3. Implementation status: Not implemented