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Implemented

RV64M integer mul/div

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$1,000 / $1,000fully funded
Done$1,000 / $1,000 - 100%
As a firmware developer, I want vemu's RV64M integer mul/div to stay accurate, tested, and documented, so that I can keep depending on integer math.

Why it matters

integer math

Summary

MUL/DIV/REM (M extension)

Scope of work

Already implemented. Harden, broaden coverage, add tests and documentation for RV64M integer mul/div. What it is: MUL/DIV/REM (M extension). Why it matters: integer math.

Current state

Status: Fully implemented. Notes / evidence: decoder M ops + JIT lowering; rv64um suite passes.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $1,000

  3. Implementation status: Implemented

  4. Delivered - counted as fully funded