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Implemented

RV64F/D floating point

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$2,000 / $2,000fully funded
Done$2,000 / $2,000 - 100%
As a firmware developer, I want vemu's RV64F/D floating point to stay accurate, tested, and documented, so that I can keep depending on floating-point firmware.

Why it matters

floating-point firmware

Summary

IEEE-754 single and double FP

Scope of work

Already implemented. Harden, broaden coverage, add tests and documentation for RV64F/D floating point. What it is: IEEE-754 single and double FP. Why it matters: floating-point firmware.

Current state

Status: Fully implemented. Notes / evidence: fpu.rs (rustc_apfloat, NaN-boxed); rv64uf + rv64ud suites pass.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $2,000

  3. Implementation status: Implemented

  4. Delivered - counted as fully funded