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Not implemented

RV64B bit-manipulation (Zba/Zbb/Zbc/Zbs)

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$0 / $8,0000% funded
Fund$8,000
$0 / $8,000 - 0%
As a firmware developer, I want vemu to finish its RV64B bit-manipulation (Zba/Zbb/Zbc/Zbs) model, so that I can depend on optimized bitwise code for production firmware, not just the common path.

Why it matters

optimized bitwise code

Summary

Zba/Zbb/Zbc/Zbs bit-manip

Scope of work

Not present today. Deliver a behavioral model of RV64B bit-manipulation (Zba/Zbb/Zbc/Zbs). Why it matters: optimized bitwise code.

Current state

Status: Not implemented.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $8,000

  3. Implementation status: Not implemented