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Implemented

RV64A atomics (LR/SC/AMO)

Priority 1 - CPU Architectures & Execution Engines / 1.7 RISC-V ISA

$1,500 / $1,500fully funded
Done$1,500 / $1,500 - 100%
As a firmware developer, I want vemu's RV64A atomics (LR/SC/AMO) to stay accurate, tested, and documented, so that I can keep depending on lock-free and SMP-capable code.

Why it matters

lock-free and SMP-capable code

Summary

LR/SC/AMO atomics

Scope of work

Already implemented. Harden, broaden coverage, add tests and documentation for RV64A atomics (LR/SC/AMO). What it is: LR/SC/AMO atomics. Why it matters: lock-free and SMP-capable code.

Current state

Status: Fully implemented. Notes / evidence: cpu.rs reservations + RvAtomic JIT helper; rv64ua suite + jit_parity pass.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $1,500

  3. Implementation status: Implemented

  4. Delivered - counted as fully funded