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Not implemented

RP1 PCIe endpoint

Raspberry Pi / Broadcom program

$0 / $7,0000% funded
Fund$7,000
$0 / $7,000 - 0%
As a device-driver developer, I want vemu to model RP1 PCIe endpoint, so that I can build and test firmware that needs the gateway for all Pi 5 RP1-hosted I/O long before the hardware is in hand.

Why it matters

The gateway for all Pi 5 RP1-hosted I/O

Summary

RP1 as a PCIe 2.0 x4 endpoint: config space, BARs, MSI/MSI-X, child-device MMIO windows

Scope of work

Not present today. Deliver a behavioral model of RP1 PCIe endpoint. What it is: RP1 as a PCIe 2.0 x4 endpoint: config space, BARs, MSI/MSI-X, child-device MMIO windows. Why it matters: The gateway for all Pi 5 RP1-hosted I/O.

Current state

Status: Not implemented. Notes / evidence: Not present.

Blocked by 2

Fund these first - this work can't be completed until they ship.

Unblocks 11

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $7,000

  3. Implementation status: Not implemented