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Not implemented

RP1 low-speed I/O (UART/I2C/SPI/PWM/I2S)

Raspberry Pi / Broadcom program

$0 / $7,0000% funded
Fund$7,000
$0 / $7,000 - 0%
As a device-driver developer, I want vemu to model RP1 low-speed I/O (UART/I2C/SPI/PWM/I2S), so that I can build and test firmware that needs pi 5 header buses and aux UART long before the hardware is in hand.

Why it matters

Pi 5 header buses and aux UART

Summary

RP1 UART, I2C, SPI, PWM and I2S controllers behind PCIe

Scope of work

Not present today. Deliver a behavioral model of RP1 low-speed I/O (UART/I2C/SPI/PWM/I2S). What it is: RP1 UART, I2C, SPI, PWM and I2S controllers behind PCIe. Why it matters: Pi 5 header buses and aux UART.

Current state

Status: Not implemented. Notes / evidence: Not present.

Blocked by 5

Fund these first - this work can't be completed until they ship.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $7,000

  3. Implementation status: Not implemented