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Not implemented

RISC-V PMP / Smepmp

Priority 7 - Security Hardware

$0 / $18,2500% funded
Fund$18,250
$0 / $18,250 - 0%
As a security engineer, I want vemu to finish its RISC-V PMP / Smepmp model, so that I can depend on RISC-V security for production firmware, not just the common path.

Why it matters

RISC-V security

Summary

RISC-V memory protection

Scope of work

Not present today. Deliver a behavioral model of RISC-V PMP / Smepmp. What it is: RISC-V memory protection. Why it matters: RISC-V security.

Current state

Status: Not implemented. Notes / evidence: No RISC-V core exists.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $18,250

  3. Implementation status: Not implemented