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Stub

Memory attributes / cacheability (MAIR/TEX)

Priority 0 - Memory System

$0 / $10,7500% funded
Fund$10,750
$0 / $10,750 - 0%
As a firmware developer, I want vemu to finish its Memory attributes / cacheability (MAIR/TEX) model, so that I can depend on correct ordering/coherency for production firmware, not just the common path.

Why it matters

Correct ordering/coherency

Summary

Honor cacheable/device/normal

Scope of work

Currently a register-only stub. Replace it with a working model of Memory attributes / cacheability (MAIR/TEX) that actually exhibits the hardware behavior. What it is: Honor cacheable/device/normal. Why it matters: Correct ordering/coherency.

Current state

Status: Stub only (registers, no behavior). Notes / evidence: AttrIndx/MAIR0-1/TEX decoded (AArch64 + PMSAv8-M) but never honored; no ordering/coherency effect.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $10,750

  3. Implementation status: Stub