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Partial

Mailbox / IPC (inter-core)

Priority 2 - Microcontroller & SoC Peripherals / 2.5 Misc on-chip blocks

$0 / $2,7500% funded
Fund$2,750
$0 / $2,750 - 0%
As a device-driver developer, I want vemu to finish its Mailbox / IPC (inter-core) model, so that I can depend on multi-core SoCs for production firmware, not just the common path.

Why it matters

Multi-core SoCs

Summary

Message passing between cores

Scope of work

Partially modeled. Complete the missing mechanics of Mailbox / IPC (inter-core). What it is: Message passing between cores. Why it matters: Multi-core SoCs.

Current state

Status: Partially implemented. Notes / evidence: Nordic IPC effectively full (16-ch loopback + cross-core + IRQ); RK mailbox delivers DAT + IRQ but CMD writes don't notify.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 6

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $2,750

  3. Implementation status: Partial