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Implemented

LSE atomics

Priority 1 - CPU Architectures & Execution Engines / 1.3 AArch64 (A64) & Cortex-A 64-bit

$1,500 / $1,500fully funded
Done$1,500 / $1,500 - 100%
As a firmware developer, I want vemu's LSE atomics to stay accurate, tested, and documented, so that I can keep depending on sMP-capable code.

Why it matters

SMP-capable code

Summary

LDADD/SWP/CAS/CASP

Scope of work

Already implemented. Harden, broaden coverage, add tests and documentation for LSE atomics. What it is: LDADD/SWP/CAS/CASP. Why it matters: SMP-capable code.

Current state

Status: Fully implemented. Notes / evidence: - .

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 1

Funding this also clears the way for the work below.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $1,500

  3. Implementation status: Implemented

  4. Delivered - counted as fully funded