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Partial

JIT frontend: riscv64 (RV64I/M/A)

Priority 1 - CPU Architectures & Execution Engines / 1.1 Execution engines

$0 / $10,5000% funded
Fund$10,500
$0 / $10,500 - 0%
As a firmware developer, I want vemu to finish its JIT frontend: riscv64 (RV64I/M/A) model, so that I can depend on speed for RISC-V for production firmware, not just the common path.

Why it matters

speed for RISC-V

Summary

RV64 - > IR

Scope of work

Partially modeled. Complete the missing mechanics of JIT frontend: riscv64 (RV64I/M/A). What it is: RV64 - > IR. Why it matters: speed for RISC-V.

Current state

Status: Partially implemented. Notes / evidence: vemu-jit-frontend-riscv64: RV64I/M + A (LR/SC/AMO) + compressed + control flow lowered to IR; CSR/privileged/FP/vector deferred to interpreter; block chaining + jit_parity/differential tests.

Blocked by 2

Fund these first - this work can't be completed until they ship.

  • Done
  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $10,500

  3. Implementation status: Partial