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Not implemented

Heterogeneous multi-core (mixed ISA)

Priority 3 - Debug, Trace & Instrumentation Hardware / 3.2 GDB / IDE debugging

$0 / $8,0000% funded
Fund$8,000
$0 / $8,000 - 0%
As a firmware debugger, I want vemu to finish its Heterogeneous multi-core (mixed ISA) model, so that I can depend on console/asymmetric SoCs for production firmware, not just the common path.

Why it matters

Console/asymmetric SoCs

Summary

Debug multiple mixed-ISA cores together

Scope of work

Not present today. Deliver a behavioral model of Heterogeneous multi-core (mixed ISA). What it is: Debug multiple mixed-ISA cores together. Why it matters: Console/asymmetric SoCs.

Current state

Status: Not implemented. Notes / evidence: Generic GDB session is monomorphized over a single arch (target_multicore.rs); all cores must share one ISA. README claim is aspirational.

Blocked by 1

Fund these first - this work can't be completed until they ship.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $8,000

  3. Implementation status: Not implemented