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Partial

Cross-core IPI / SGI affinity delivery

Priority 2 - Interrupt & Exception Controllers

$0 / $4,0000% funded
Fund$4,000
$0 / $4,000 - 0%
As a RTOS developer, I want vemu to finish its Cross-core IPI / SGI affinity delivery model, so that I can depend on SMP for production firmware, not just the common path.

Why it matters

SMP

Summary

Inter-processor interrupts

Scope of work

Partially modeled. Complete the missing mechanics of Cross-core IPI / SGI affinity delivery. What it is: Inter-processor interrupts. Why it matters: SMP.

Current state

Status: Partially implemented. Notes / evidence: SGIs modeled per-core; no real multi-core delivery.

Blocked by 1

Fund these first - this work can't be completed until they ship.

Unblocks 3

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $4,000

  3. Implementation status: Partial