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Partial

Clock tree (RCC/CRU/CLOCK)

Priority 2 - Microcontroller & SoC Peripherals / 2.6 Clock / reset / power

$0 / $4,0000% funded
Fund$4,000
$0 / $4,000 - 0%
As a device-driver developer, I want vemu to finish its Clock tree (RCC/CRU/CLOCK) model, so that I can depend on correct timing and peripheral clocks for production firmware, not just the common path.

Why it matters

Correct timing & peripheral clocks

Summary

PLLs, muxes, dividers, gates

Scope of work

Partially modeled. Complete the missing mechanics of Clock tree (RCC/CRU/CLOCK). What it is: PLLs, muxes, dividers, gates. Why it matters: Correct timing & peripheral clocks.

Current state

Status: Partially implemented. Notes / evidence: Ready/selection bits + Nordic clock-task FSM modeled; no frequency math (no Hz computed) and no gating enforcement (EN bits unconsumed; RK clock_is_gated() is dead code).

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 30

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $4,000

  3. Implementation status: Partial