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Stub

Camera ISP / MIPI CSI pipeline

Priority 4 - Hardware Accelerators

$0 / $21,7500% funded
Fund$21,750
$0 / $21,750 - 0%
As an edge-AI / multimedia developer, I want vemu to finish its Camera ISP / MIPI CSI pipeline model, so that I can depend on vision SoCs for production firmware, not just the common path.

Why it matters

Vision SoCs

Summary

Image signal processing

Scope of work

Currently a register-only stub. Replace it with a working model of Camera ISP / MIPI CSI pipeline that actually exhibits the hardware behavior. What it is: Image signal processing. Why it matters: Vision SoCs.

Current state

Status: Stub only (registers, no behavior). Notes / evidence: RK VICAP/ISP/CSI: register bags; VICAP fetches a frame from the camera source but discards it (frame-done IRQ only, no pixel DMA to RAM).

Blocked by 2

Fund these first - this work can't be completed until they ship.

  • Done
  • Done
Unblocks 3

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $21,750

  3. Implementation status: Stub