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Not implemented

Cache model (I/D, lines, coherency)

Priority 0 - Memory System

$0 / $15,5000% funded
Fund$15,500
$0 / $15,500 - 0%
As a firmware developer, I want vemu to finish its Cache model (I/D, lines, coherency) model, so that I can depend on perf and coherency behavior for production firmware, not just the common path.

Why it matters

Perf & coherency behavior

Summary

Model caches & maintenance ops

Scope of work

Not present today. Deliver a behavioral model of Cache model (I/D, lines, coherency). What it is: Model caches & maintenance ops. Why it matters: Perf & coherency behavior.

Current state

Status: Not implemented. Notes / evidence: No caches modeled.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done
Unblocks 3

Funding this also clears the way for the work below.

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $15,500

  3. Implementation status: Not implemented