← Back to roadmap
Not implemented

Bus arbitration / contention / wait-states

Priority 0 - Memory System

$0 / $9,7500% funded
Fund$9,750
$0 / $9,750 - 0%
As a firmware developer, I want vemu to finish its Bus arbitration / contention / wait-states model, so that I can depend on realistic timing for production firmware, not just the common path.

Why it matters

Realistic timing

Summary

Multi-master timing

Scope of work

Not present today. Deliver a behavioral model of Bus arbitration / contention / wait-states. What it is: Multi-master timing. Why it matters: Realistic timing.

Current state

Status: Not implemented. Notes / evidence: All access O(1).

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $9,750

  3. Implementation status: Not implemented