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Not implemented

ASID/VMID-tagged TLB

Priority 0 - Memory System

$0 / $9,7500% funded
Fund$9,750
$0 / $9,750 - 0%
As a firmware developer, I want vemu to finish its ASID/VMID-tagged TLB model, so that I can depend on context-switch perf fidelity for production firmware, not just the common path.

Why it matters

Context-switch perf fidelity

Summary

Tagged translation caching

Scope of work

Not present today. Deliver a behavioral model of ASID/VMID-tagged TLB. What it is: Tagged translation caching. Why it matters: Context-switch perf fidelity.

Current state

Status: Not implemented. Notes / evidence: Full-flush only.

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $9,750

  3. Implementation status: Not implemented