← Back to roadmap
Stub

ARMv7-M BusFault

Priority 2 - Interrupt & Exception Controllers

$0 / $5,5000% funded
Fund$5,500
$0 / $5,500 - 0%
As a RTOS developer, I want vemu to finish its ARMv7-M BusFault model, so that I can depend on memory-error handling for production firmware, not just the common path.

Why it matters

Memory-error handling

Summary

External bus error - > fault

Scope of work

Currently a register-only stub. Replace it with a working model of ARMv7-M BusFault that actually exhibits the hardware behavior. What it is: External bus error - > fault. Why it matters: Memory-error handling.

Current state

Status: Stub only (registers, no behavior). Notes / evidence: Vector + SHPR priority + CFSR.BFSR field exist, but nothing ever raises BusFault (no precise/imprecise bus-error source; BFAR never written).

Blocked by 1

Fund these first - this work can't be completed until they ship.

  • Done

Activity log

  1. Feature defined and added to the roadmap

  2. Funding goal set to $5,500

  3. Implementation status: Stub